--- Quote Start ---
Please post a schematic/drawing of your proposed interface.
--- Quote End ---
hi. apologies, i should have added the schematic before.
NPN transistor: NXP BDT125. Max I_c is 6.5mA. Its switching is 2Ghz so it should not give much delay. I will probably add a speed-up capacitor if i need more performance.
X1-40 goes to the GPIO.
My plan:
RB_0=93.5kohm.
RE_0=3.3 kohm
GND is connected to the GND pin of the ATA header and and the V_cc to the 3.3 V pin
I_b comes out to be 0.019 mA. And I_c, comes out to be 0.75 mA.
I can probably change the resistors and and the V_cc to 5V and get I_c to be 3.3 mA, but I rather not if I can get away with it.
my concern was if the GPIO will be sensitive enough to react to the change in voltage at 50ns.
cheers.
PS: i did some additional googling, and I came up with this pdf which states the JEDEC Standard No. 8-5A.01 using by the GPIO and the file has an Absolute maximum continuous rating of as +/- 20 mA. the file also specifies normal operating conditions where It says I_i (Input current) for both high and low as +/-15micro amp.
This is all good. however, if that is specification of JEDEC Standard No. 8-5A.01,, i was hoping someone to confirm that this would work with 0.75mA "source strength". I would hate to make a PCB board only to blow up all the transistors :(
Honored Contributor
