Altera_Forum
Honored Contributor
15 years agoMaximum Number of DDR2 SDRAM Interfaces Supported per FPGA with Cyclone IV
Hello,
I am trying to use the Cyclone IV E with DDR2 SDRAM interfaces. I have a question with the Maximum Number of DDR2 SDRAM Interfaces Supported per FPGA for Cyclone IV E in the documentation (Section III. System Performance Specifications) : When it is said that on top side, for example, the Maximum Number of DDR2 SDRAM Interfaces is "one x 48 interfaces" or "two x 8 interfaces" it is not equivalent ! You can only reach an equivalent of "one x 16 interfaces" in the second case ? I don't clearly understand what is a "x48" or "x8 interfaces". Is it the number of bits of Data bus ? Does that mean that you can only use on this side either one DDR2 SDRAM interface with a 48-width of Data Bus, or two with an only 8-width of Data Bus ? Thanks