Maximum Number of DDR2 SDRAM Interfaces Supported per FPGA with Cyclone IV

You didn't mention which Cyclone IV E device you are using.

Table 7-2 of the user's guide is useful:

http://www.altera.com/literature/hb/cyclone-iv/cyiv-5v1-02.pdf

Yes the width refers to the number of bits on the data bus.

There are usually 3 constraints to consider for the limitation on number of memory controllers you can support:

1 - I/O pin limitations (this is the number of DQ groups available, and don't forget command / address pins).

2 - PLL limitations (you need a PLL per controller I believe).

3 - Internal resource utilization.

So on a EP4CE115 device in the 780 pin package; you could presumably have 6 x8/x9 groups on the top and/or bottom of the device. So to me this means you could have:

1 x48 DDR2 controller (6 groups of x8/x9)

2 x8/x9 DDR2 controllers (1 groups of x8/x9 each)

2 x16/x18 DDR2 controllers (2 groups of x8/x9 each)

2 x24/x27 DDR2 controllers (3 groups of x8/x9 each)

Now could you do 3 x8/9 interfaces. My gut tells me know. I'm thinking the PLL clocking is going to get hairy.

Jake