Forum Discussion
New ContributorMax10 Security
Regular ContributorHello,
Max10 only supports limited design security feature. It can't implement design authentication or security key programming like Agilex devices.
Below link has the supported feature list:
regards,
Farabi
a1990What is the correct approach to get the FPGA content secured? This means making sure it cannot be read out via JTAG. Therefore, how can the read-back process be prevented?
- a1990
I need an answer please....
- Farabi_Altera
Hello,
MAX10 is not supported in Quartus Pro.
MAX10 dont support design security features like authentication, security key programming etc.
It only supports design encryption. Please refer here : https://www.intel.com/content/www/us/en/docs/programmable/683865/current/configuration-design-security.html
regards,
Farabi
FakhrulA_alteraHi a1990,
Frank is right. MAX 10 supports multiple security features you can use:
- 128-bit AES encrypted configuration
- Secure JTAG mode to block readback
For your goals maybe you could try:
- Enable bitstream encryption
- Set JTAG to Secure mode to prevent readback
- Program the CFM protection bits
MAX 10 does not support bitstream authentication or key storage beyond encryption. Storing the bitstream in internal flash is fine if you enable encryption and protections. If you need authenticated boot, consider a device that supports it.
Please review the MAX® 10 FPGA Configuration User Guide for details.
Regards,
Fakhrul- FakhrulA_altera
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