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Altera_Forum
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10 years ago

MAX10 ADC doesn't start during power on

I'm using MAX10 ADC to measure on board voltages. The ADC IP operates normally when the design was programmed using JTAG USB Byte Blaster with SOF file. When same design is programmed using POF file, only ADC IP doesn't run while other logic operates normally. I generated ADC IP as "ADC Control Core Only". Anyone ran into this issue?

Thanks,

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  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Do the power supplies you are using for the device meet the requirements for MAX 10? Refer to the "max 10 power management user guide (https://www.altera.com/literature/hb/max-10/ug_m10_pwr.pdf)".

    --- Quote Start ---

    If the ramp time, tRAMP, is not met, the MAX 10 device I/O pins and programming registers remain tristated, during which device configuration could fail.

    --- Quote End ---

    It does not state exactly how this "could" fail. However, it may well be possible that partial configuration - of the logic - might occur and the ADC suffers. Subsequently programming it with a .sof, once the rails are all up and steady, could rectify this.

    So, refer to figure 2-3 on page 2-6 and confirm your device rails comply.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I have the same issue, with a 10m50 MAX 10 adc. The .sof works fine but the .pofadc does not! YES I am using the correct files. I connected VCCIO1A and B to the same rail, but no success. I have noticed that the 'power down' flag is set, what is that? I found this in the Verilog files for the adc.

    I have tried a DECA board and it works fine, I have also tried a BeMicro board and it works fine in both .sof and .pof modes.

    NOTE: the power rails for the DECA and BEMicro are different, I tried both on my board with no luck...

    YUCK....
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Thanks for the reply Alex.

    The POF is generated from SOF. This was my time running into this issue. I actually debugged Altera's IP until I got down to ADC hard IP, and this indicated that ADC hard IP was not generated correct clocks. So, I started to check the schematic, and I found the issue. The board designer connected VCCIO1A and VCCIO1B to wrong rail. I'm not sure how this rail pins are used for ADC, but it's related. When I tried my design on DECA development board, the POF file does work. This concludes this bug.

    I hope this thread can be useful for other engineers.

    Regards,
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Are you convinced you're using the right .sof to generate your .pof programming file? If you have part of your design behaving as expected might you have incorrectly used a previous, older .sof file?

    I've never experienced a .sof / .pof discrepancy as you describe.

    Cheers,

    Alex