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Altera_Forum
Honored Contributor
9 years agoThanks for the reply Alex.
The POF is generated from SOF. This was my time running into this issue. I actually debugged Altera's IP until I got down to ADC hard IP, and this indicated that ADC hard IP was not generated correct clocks. So, I started to check the schematic, and I found the issue. The board designer connected VCCIO1A and VCCIO1B to wrong rail. I'm not sure how this rail pins are used for ADC, but it's related. When I tried my design on DECA development board, the POF file does work. This concludes this bug. I hope this thread can be useful for other engineers. Regards,