Honored Contributorhi,
my question is quite general for FPGA devices. i have a matlab code for a BP FIR filter with a very large number of coefficients, from 2k to 20k and above. if i would implement the filter on a simple altera device, will it work in a reasonable time? or is it a must to cut the filter into a cascade of FIR with much less coefficients?
Honored ContributorThe number of filter coefficients is related to the transition bandwidth, i.e., the space between the passband and stopband, a large number of filter coefficients implies a very sharp cut-off.
If you could explain your filtering requirements, and your filter design, then readers of this forum could review your design. If you are using a filter to reduce the bandwidth of your signal, then you should be looking at combining filtering and decimation, i.e., use multi-rate signal processing. There is no single "right" solution, since the range of options changes depending on the bandwidth of the signal you are processing relative to the clock rate of the FPGA you are using. Here's some notes you can review: http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104paper_hawkins.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104slides_hawkins.pdf Cheers, DaveHonored ContributorYes, I agree with Dave's answer. A decimating multi-rate filter is the best approach if your sample rate and data rate allows it.
You can easily run a FIR in modern FPGA's at 100-150 MHz. Above 200 MHz operation is very possible, but care in timing closure and structure must be taken. If your filters are symmetrical, you can reduce the number of multipliers required in 1/2. (Just add a summing node in front of the multipliers, and pipe the data through correctly) If your filters are also decimating, you can further reduce the number of multipliers required by the decimation factor. (basically you cycle through N coefficients as it's decimating.) The exact method you use, and is it possible, will depend greatly on what you are attempting to achieve. PeteHonored Contributorhi,
tnx for the comments, i'll read the notes. the filter supossed to be a very narrow high prefomence band pass (based on a paper), that's why it has this huge amount of coefficients (as dave said). it is a type I fir so it is symmmetrical with and odd length. the writers of the paper implement the filter with a TI 8 or 32 core DSP, and we wondered if its possible in a FPGA as is.Honored ContributorHonored ContributorIt will depend on many things : what data rate you need, the width of your coefficients (fixed point - If you want floating point, forget it now at the scales you're talking about), what the target device is etc.
For example, if you were ok with 16 bit resolution (32 bit multipler output), a top of the range Stratix V GS has nearly 4000 18 bit multipliers. With efficient design, these can be clocked at >300 MHz, so assuming a 75MHz data rate, you can share these mults between 4 paths, giving you essentiall 16000 parrallel mults. At a slower data rate this could be even more. But this part is at the top end (and therefore v expensive. ) This is of course theory, and in practice doing this would require a lot of engineering effort. It really comes down to what you can afford and how you can compromise in the algorithm.Honored ContributorHonored ContributorThe original post is asking for an implementation in a "simple Altera device", so high end Stratix doesn't seem to be an option.
It's quite easy to get infeasible FIR parameters in Matlab, we should go back to the filter specification to understand what might be a reasonable way to implement it.
