Max number of FIR filter coefficients

Yes, I agree with Dave's answer. A decimating multi-rate filter is the best approach if your sample rate and data rate allows it.

You can easily run a FIR in modern FPGA's at 100-150 MHz. Above 200 MHz operation is very possible, but care in timing closure and structure must be taken. If your filters are symmetrical, you can reduce the number of multipliers required in 1/2.

(Just add a summing node in front of the multipliers, and pipe the data through correctly)

If your filters are also decimating, you can further reduce the number of multipliers required by the decimation factor. (basically you cycle through N coefficients as it's decimating.)

The exact method you use, and is it possible, will depend greatly on what you are attempting to achieve.

Pete