Max number of FIR filter coefficients

It will depend on many things : what data rate you need, the width of your coefficients (fixed point - If you want floating point, forget it now at the scales you're talking about), what the target device is etc.

For example, if you were ok with 16 bit resolution (32 bit multipler output), a top of the range Stratix V GS has nearly 4000 18 bit multipliers. With efficient design, these can be clocked at >300 MHz, so assuming a 75MHz data rate, you can share these mults between 4 paths, giving you essentiall 16000 parrallel mults. At a slower data rate this could be even more. But this part is at the top end (and therefore v expensive. )

This is of course theory, and in practice doing this would require a lot of engineering effort. It really comes down to what you can afford and how you can compromise in the algorithm.