Honored Contributor
Honored ContributorThe number of filter coefficients is related to the transition bandwidth, i.e., the space between the passband and stopband, a large number of filter coefficients implies a very sharp cut-off.
If you could explain your filtering requirements, and your filter design, then readers of this forum could review your design. If you are using a filter to reduce the bandwidth of your signal, then you should be looking at combining filtering and decimation, i.e., use multi-rate signal processing. There is no single "right" solution, since the range of options changes depending on the bandwidth of the signal you are processing relative to the clock rate of the FPGA you are using. Here's some notes you can review: http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104paper_hawkins.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104slides_hawkins.pdf Cheers, Dave
