Forum Discussion

Occasional Contributor

3 years ago

Solved

MAX 7000B (only some packages in Quartus 13.0sp1)

I'm trying to design a board for a EPM7032BLC44-7 (PLCC package) but Quartus 13.0sp1 only has support for EPM7032BTC44-7 (TQFP package) which has a different pinout.

I haven't yet found a nice grid which says which specific chips are supported by which specific versions of (MAXII, Quartus II, Quartus Prime).

Any idea how I would compile for the PLCC package?

ak6dn

3 years ago

So it appears that the issue is only in the graphical support aspect of the Quartus 13.0sp1 tool.

I have as design that normally uses an EPM7064S in PLC44 and I already have all the .qpf/.qsf/.sdc files for it.
Normally I just run the command line tools and bypass the graphical aspect of Quartus.

As it happens, the EPM7064S and EPM7064B have the exact same PLC44 pinout.
So, in the project top level .qsf file, I changed the entries to be:

set_global_assignment -name FAMILY MAX7000B
set_global_assignment -name DEVICE "EPM7064BLC44-7"

and then ran the full design creation script. It completed successfully!

So it looks like if you bypass the graphical menu system (which appears to be mis-configured for the MAX7000B series)
the back end tools still do the right thing in generating the programming file.

Here is the design .fit.summary file:

Fitter Status : Successful - Tue Jul 19 00:22:29 2022
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : EPM7064B
Top-level Entity Name : EPM7064B
Family : MAX7000B
Device : EPM7064BLC44-7
Timing Models : Final
Total macrocells : 60 / 64 ( 94 % )
Total pins : 36 / 36 ( 100 % )

And the design .asm.rpt file:

Assembler report for EPM7064B
Tue Jul 19 00:22:31 2022
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Assembler Summary
  3. Assembler Settings
  4. Assembler Generated Files
  5. Assembler Device Options: E:/Projects/altera_test/EPM7064B-PL44/par/EPM7064B.pof
  6. Assembler Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------+
; Assembler Summary                                             ;
+-----------------------+---------------------------------------+
; Assembler Status      ; Successful - Tue Jul 19 00:22:31 2022 ;
; Revision Name         ; EPM7064B                              ;
; Top-level Entity Name ; EPM7064B                              ;
; Family                ; MAX7000B                              ;
; Device                ; EPM7064BLC44-7                        ;
+-----------------------+---------------------------------------+


+---------------------------------------------------------------------------------------------------------+
; Assembler Settings                                                                                      ;
+-----------------------------------------------------------------------------+-----------+---------------+
; Option                                                                      ; Setting   ; Default Value ;
+-----------------------------------------------------------------------------+-----------+---------------+
; Use smart compilation                                                       ; On        ; Off           ;
; Configuration device auto user code                                         ; On        ; Off           ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On        ; On            ;
; Enable compact report table                                                 ; Off       ; Off           ;
; Compression mode                                                            ; Off       ; Off           ;
; Clock source for configuration device                                       ; Internal  ; Internal      ;
; Clock frequency of the configuration device                                 ; 10 MHZ    ; 10 MHz        ;
; Divide clock frequency by                                                   ; 1         ; 1             ;
; Auto user code                                                              ; Off       ; Off           ;
; Security bit                                                                ; Off       ; Off           ;
; Use configuration device                                                    ; On        ; On            ;
; Generate Tabular Text File (.ttf) For Target Device                         ; Off       ; Off           ;
; Generate Raw Binary File (.rbf) For Target Device                           ; Off       ; Off           ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off       ; Off           ;
; Hexadecimal Output File start address                                       ; 0         ; 0             ;
; Hexadecimal Output File count direction                                     ; Up        ; Up            ;
; Generate Serial Vector Format File (.svf) for Target Device                 ; Off       ; Off           ;
; Generate In System Configuration File (.isc) for Target Device              ; Off       ; Off           ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off       ; Off           ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off       ; Off           ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On        ; On            ;
; In-System Programming Default Clamp State                                   ; Tri-state ; Tri-state     ;
+-----------------------------------------------------------------------------+-----------+---------------+


+--------------------------------------------------------+
; Assembler Generated Files                              ;
+--------------------------------------------------------+
; File Name                                              ;
+--------------------------------------------------------+
; E:/Projects/altera_test/EPM7064B-PL44/par/EPM7064B.pof ;
+--------------------------------------------------------+


+----------------------------------------------------------------------------------+
; Assembler Device Options: E:/Projects/altera_test/EPM7064B-PL44/par/EPM7064B.pof ;
+----------------+-----------------------------------------------------------------+
; Option         ; Setting                                                         ;
+----------------+-----------------------------------------------------------------+
; Device         ; EPM7064BLC44-7                                                  ;
; JTAG usercode  ; 0x00000000                                                      ;
; Checksum       ; 0x000C0707                                                      ;
+----------------+-----------------------------------------------------------------+


+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, Altera MegaCore Function License 
    Info: Agreement, or other applicable license agreement, including, 
    Info: without limitation, that your use is for the sole purpose of 
    Info: programming logic devices manufactured by Altera and sold by 
    Info: Altera or its authorized distributors.  Please refer to the 
    Info: applicable agreement for further details.
    Info: Processing started: Tue Jul 19 00:22:30 2022
Info: Command: quartus_asm EPM7064B --write_settings_files=off
Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 4510 megabytes
    Info: Processing ended: Tue Jul 19 00:22:31 2022
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01

7 Replies

AqidAyman_Altera

Regular Contributor

3 years ago

Hi Kevin,

Is there any other PLCC package available in the Available Device List?

In the meantime, you can try the following method:

Target a different device with the same pinout for your project or design file, and save the project. Open the .QSF file and change the device selection line to match your device. Save the file, and try to compile. Check the report if it chose that part.

Regards,

Aqid Ayman

ak6dn
Regular Contributor
3 years ago
Well, it looks like there is an error in the Quartus 13.0sp1 web tool database files, or the menu files.

Three screen shots:

1) Screenshot of quartus/common/devinfo/max7000b directory. There are PLC44 package files for 7032b, 7064b.

2) Screenshot of quartus device selection window for MAX7000B family. Notice PLCC packaging option is not available.

3) Screenshot of quartus device selection window for MAX7000AE family. Notice PLCC packaging option IS available.
- DrNickels
  Occasional Contributor
  3 years ago
  Yep, I see the same thing on my end.

DrNickels

Occasional Contributor

3 years ago

Nope, the Assignments/Device menu is showing no PLCC packages in the MAX7000B family. If I select the MAX7000S or MAX7000AE families as @ak6dn suggests, they show up.

ak6dn

Regular Contributor

3 years ago

So it appears that the issue is only in the graphical support aspect of the Quartus 13.0sp1 tool.

I have as design that normally uses an EPM7064S in PLC44 and I already have all the .qpf/.qsf/.sdc files for it.
Normally I just run the command line tools and bypass the graphical aspect of Quartus.

As it happens, the EPM7064S and EPM7064B have the exact same PLC44 pinout.
So, in the project top level .qsf file, I changed the entries to be:

set_global_assignment -name FAMILY MAX7000B
set_global_assignment -name DEVICE "EPM7064BLC44-7"

and then ran the full design creation script. It completed successfully!

So it looks like if you bypass the graphical menu system (which appears to be mis-configured for the MAX7000B series)
the back end tools still do the right thing in generating the programming file.

Here is the design .fit.summary file:

Fitter Status : Successful - Tue Jul 19 00:22:29 2022
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : EPM7064B
Top-level Entity Name : EPM7064B
Family : MAX7000B
Device : EPM7064BLC44-7
Timing Models : Final
Total macrocells : 60 / 64 ( 94 % )
Total pins : 36 / 36 ( 100 % )

And the design .asm.rpt file:

Assembler report for EPM7064B
Tue Jul 19 00:22:31 2022
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Assembler Summary
  3. Assembler Settings
  4. Assembler Generated Files
  5. Assembler Device Options: E:/Projects/altera_test/EPM7064B-PL44/par/EPM7064B.pof
  6. Assembler Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------+
; Assembler Summary                                             ;
+-----------------------+---------------------------------------+
; Assembler Status      ; Successful - Tue Jul 19 00:22:31 2022 ;
; Revision Name         ; EPM7064B                              ;
; Top-level Entity Name ; EPM7064B                              ;
; Family                ; MAX7000B                              ;
; Device                ; EPM7064BLC44-7                        ;
+-----------------------+---------------------------------------+


+---------------------------------------------------------------------------------------------------------+
; Assembler Settings                                                                                      ;
+-----------------------------------------------------------------------------+-----------+---------------+
; Option                                                                      ; Setting   ; Default Value ;
+-----------------------------------------------------------------------------+-----------+---------------+
; Use smart compilation                                                       ; On        ; Off           ;
; Configuration device auto user code                                         ; On        ; Off           ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On        ; On            ;
; Enable compact report table                                                 ; Off       ; Off           ;
; Compression mode                                                            ; Off       ; Off           ;
; Clock source for configuration device                                       ; Internal  ; Internal      ;
; Clock frequency of the configuration device                                 ; 10 MHZ    ; 10 MHz        ;
; Divide clock frequency by                                                   ; 1         ; 1             ;
; Auto user code                                                              ; Off       ; Off           ;
; Security bit                                                                ; Off       ; Off           ;
; Use configuration device                                                    ; On        ; On            ;
; Generate Tabular Text File (.ttf) For Target Device                         ; Off       ; Off           ;
; Generate Raw Binary File (.rbf) For Target Device                           ; Off       ; Off           ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off       ; Off           ;
; Hexadecimal Output File start address                                       ; 0         ; 0             ;
; Hexadecimal Output File count direction                                     ; Up        ; Up            ;
; Generate Serial Vector Format File (.svf) for Target Device                 ; Off       ; Off           ;
; Generate In System Configuration File (.isc) for Target Device              ; Off       ; Off           ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off       ; Off           ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off       ; Off           ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On        ; On            ;
; In-System Programming Default Clamp State                                   ; Tri-state ; Tri-state     ;
+-----------------------------------------------------------------------------+-----------+---------------+


+--------------------------------------------------------+
; Assembler Generated Files                              ;
+--------------------------------------------------------+
; File Name                                              ;
+--------------------------------------------------------+
; E:/Projects/altera_test/EPM7064B-PL44/par/EPM7064B.pof ;
+--------------------------------------------------------+


+----------------------------------------------------------------------------------+
; Assembler Device Options: E:/Projects/altera_test/EPM7064B-PL44/par/EPM7064B.pof ;
+----------------+-----------------------------------------------------------------+
; Option         ; Setting                                                         ;
+----------------+-----------------------------------------------------------------+
; Device         ; EPM7064BLC44-7                                                  ;
; JTAG usercode  ; 0x00000000                                                      ;
; Checksum       ; 0x000C0707                                                      ;
+----------------+-----------------------------------------------------------------+


+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, Altera MegaCore Function License 
    Info: Agreement, or other applicable license agreement, including, 
    Info: without limitation, that your use is for the sole purpose of 
    Info: programming logic devices manufactured by Altera and sold by 
    Info: Altera or its authorized distributors.  Please refer to the 
    Info: applicable agreement for further details.
    Info: Processing started: Tue Jul 19 00:22:30 2022
Info: Command: quartus_asm EPM7064B --write_settings_files=off
Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 4510 megabytes
    Info: Processing ended: Tue Jul 19 00:22:31 2022
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01

AqidAyman_Altera
Regular Contributor
3 years ago
Hi Kevin,

Just want to check on you for this issue, did you manage to compile for the PLCC package as per method suggested by @ak6dn ?

Regards,
Aqid Ayman
- DrNickels
  Occasional Contributor
  3 years ago
  No, I ended up using the TQPF package and haven't gone back to the programming phase.

Forum Discussion

MAX 7000B (only some packages in Quartus 13.0sp1)

7 Replies

Recent Discussions

Cyclone IV E – PLL Power Track Width Recommendation Clarification

Operating temperature for 10M08DCF256A7G

System PLL of Agliex5 PCIE example design cannot be locked after configuration

Download links not working

JTAG Chain Broken on Agilex 7-I Dev Kit