ak6dn
Regular ContributorJoined 7 years ago
User Profile
Regular Contributor
User Widgets
Contributions
Re: Tri-state bus data bus delayed
Are you referencing actual clocked registers? Or latches? Quartus can move registers around and can replicate and/or merge registers as it sees fit. If you write some clocked logic equations where you inadvertently don't always assign a value to the output Quartus may infer a latch and insert it. So be very specific in your terminology of register vs latch when describing your logic.7.6KViews1like1CommentRe: Tri-state bus data bus delayed
You don't say what version of Quartus or even what device you are using. Or if your tr-state bus is on chip or off chip. That being said, physically any FPGA I am aware of does not have a true on-chip tri-state bus per se, but it is implemented with logic and multiplexors. So logically your Verilog/VHDL may be written as a tri-state bus, but during synthesis it is turned into logic, specifically an N:1 multiplexor for the driver function. Depending on how wide your N:1 mux is (ie, number of discrete source drivers) and how fast your clock rate is, it might just be the logic delay is longer than a clock cycle.7.7KViews0likes1CommentRe: Next gen processor FS90, right direction?
Absolutely silly. And completely unrelated to FPGAs, mostly. Not even talking about implementing such code in an FPGA. Just someone's pet project. "Yes though 10-100 times faster is a noticeable thing." ... No it is not, if you only do it 1% of the time.3KViews0likes1CommentRe: Next gen processor FS90, right direction?
What percentage of most applications are spent doing fractional math? I suspect it is in the single digits, i.e. less than 10%. Probably closer to 1%. Optimizing 1% of your code to execute 10X (or even 100X) faster is not going to be noticeable. What you have proposed might make an interesting technical paper or senior project, but is not a practical commercial application.3.1KViews0likes4CommentsRe: DE0 Nano and windows 11
Well, if you go to the operating system support page: https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-software/os-support.html And read the ReadMe.txt files for recent Quartus versions, Quartus Prime Pro v22.3 is the first version that lists Windows 11 as a supported environment. All prior versions list Windows 10 only.2KViews1like1CommentRe: Error (169281): There are 257 IO input pads in the design, but only 224 IO input pad locations avail
What version of Quartus? What device/family? How many top level I/Os does your code define? You need to provide a lot more info before anybody can provide any significant help.2.3KViews0likes1CommentRe: Out of memory in module quartus_syn.exe
You need to provide a lot more info about your configuration. What version of Quartus? What is the target FPGA device? What Operating System? What are you compiling? Is it all your own verilog, or is it IP modules? Be as specific as possible about each of these topics, then folks will be able to provide useful suggestions.1.4KViews0likes0Comments