Forum Discussion
Occasional ContributorTri-state bus data bus delayed
Occasional ContributorIf this "shifting" of registers back and forth along the data path during synthesis happens - I would understand if this was done with a known expected latch in the actual design. But as can be seen in the RTL the latching of the data occurs in the Write and Read state machine blocks ! After the data leaves these SM blocks - there are no other registers in the design !
Why does the Quartus Synthesizer add this additional latch to implement the tri state buffer AND is there any way to prevent the synthesizer from doing this ?
Regular ContributorAre you referencing actual clocked registers? Or latches?
Quartus can move registers around and can replicate and/or merge registers as it sees fit.
If you write some clocked logic equations where you inadvertently don't always assign a value to the output Quartus may infer a latch and insert it.
So be very specific in your terminology of register vs latch when describing your logic.
- SDavi9
Sorry I was referring to the addition of a clocked register.
The problem can be seen clearly in the RTL representation attached : USB429 - usbD birectional output implementation - RTL.jpg
Where the Tri State buffer is connected directly to the output pin usbD[31..0]
Then in the Technology Map View shown in : USB429 - usbD birectional output implementation - Technology Map Viewer 1.jpg
and then expanded in : USB429 - usbD birectional output implementation - Technology Map Viewer 2.jpg
That a clocked register for some reason has been placed between my Mux and the Tri state buffer for some reason.
??????
