Honored ContributorHi Folks,
I am using MAX-10 FPGA (P/N: 10M02SCU169C8G) in my design. Application of the FPGA is to manage board controls and power sequencing. Here clock input information is limited in guideline. I have attached the snapshot of the design connection guideline for reference. Please suggest what is the input frequency required for the FPGA and which pin need to be used for clock inputs? Thanks VT
Honored ContributorThe clock frequency can be anything up to the maximum specified in the datasheet - in your case 402MHz (providing an appropriate clock network is used).
Drive the clock into any of the 'CLKxx' pins, listed in the 'Optional Function(s)' column, in the 10m02sc device pinout (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/dp/max-10/10m02sc.pdf). Cheers, AlexHonored ContributorThanks Alex,
My SoC is providing only 32KHz, but this will be an issue to implement the logic in high rates right ? I mean like I2C, JTAG interface etc? Also for my understanding purpose, how it will be wrong if we drive the clock to DPCLK pin, I am asking this because it is shown to use as " global clock network for high fan-out control signals" Thanks VTHonored Contributor32kHz is not going to be high enough, no. You're I2C is likely to operate at a minimum of 100kHz. Whilst this is not a particularly 'high rate', you'll need a clock speed higher than that to operate the logic for it.
You shouldn't need to worry about anything JTAG. I wouldn't expect you to need to supply any clock, as part of your design, for that. Yes, you can use the DPCLK pins. However, they cannot drive a PLL (should you end up wishing to use one). Any of the 'CLKxx' pins will also allow you to to drive a PLL as well as being able to drive suitable global routing resources. Cheers, AlexHonored ContributorThanks Alex :-)
