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Altera_Forum
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9 years ago

MAX-10 Input clock information

Hi Folks, I am using MAX-10 FPGA (P/N: 10M02SCU169C8G) in my design. Application of the FPGA is to manage board controls and power sequencing. Here clock input information is limit...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Thanks Alex,

My SoC is providing only 32KHz, but this will be an issue to implement the logic in high rates right ?

I mean like I2C, JTAG interface etc?

Also for my understanding purpose, how it will be wrong if we drive the clock to DPCLK pin, I am asking this because it is shown to use as " global clock network for high fan-out control signals"

Thanks

VT