Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorMAX 10 in place of Cyclone IV
Well, this seems fine to me, but I thought I'd ask the experts before doing it:
I've made a VHDL design that's currently working on a Cyclone IV E. It uses the internal RAM (dual port mode), about 15 I/O pins, and... thats it! It's using only 9% of the Cyclone IV E's logic elements. I then looked for a smaller FPGA that can do what I need, and found the MAX 10 10M02. It has all the RAM I need supporting dual port mode, needs only one single 3.3V supply (instead of 3 different voltages that the Cyclone IV needs), and has internal FLASH, not needing an external configuration chip like the Cyclone IV needs. It can store it's configuration (the "VHDL code") inside it. Not to mention its cheaper! So, I created a new project on Quartus Prime, set it to the MAX 10 chip, copied the same VHDL code from the Cyclone IV project with only minor adjustments (RAM address length and such), added the dual port RAM IP, and it compiled just fine. In fact, the compilation report says I'm using only 18% of the MAX 10's logic elements. Well, when something is too good to be true, maybe it isn't. I don't have a MAX 10 here to test, so I'm designing the final board with the MAX 10 instead of the Cyclone IV, assuming it will work. I don't see a reason for why it won't, but since I'm pretty new with Altera's FPGAs I thought I'd come ask: If a design that doesn't require any extreme parameters gets ported from a Cyclone IV to a MAX 10, should it work just fine? Main clock will be 50MHz.20 Replies
Altera_Forumi don't see why not :) But if you really want to check it out on hardware, the evaluation kit isn't that expensive either: https://www.buyaltera.com/partdetail?partid=4976140
That is a bigger brother version (10M08) but it should behave just the same as the rest of the line-up- Altera_Forum
MAX10 is also my first choice for small designs like the mentioned one.
- Altera_Forum
Good to know :)
Just to make sure: - The MAX 10 10M02 has configuration FLASH memory to cover a VHDL code that uses all of its resources, correct? Because I saw that it has a little bit of "User FLASH memory", but I assume it's a separate FLASH memory just for any possible user data (if any), and not for storing the configuration. Is that right? - I also saw that the 10M02 has a built-in 116MHz oscillator. Is that true? So I don't even need an external XTAL if my design don't need a very precise clock signal? - Altera_Forum
The built-in flash is divided up into CFM (configuration flash memory) and UFM (user flash memory). Depending on the device, you can organize the UFM and CFM in different ways. The CFM is sized to be able to program the entire device.
- Altera_Forum
According to: https://www.altera.com/en_us/pdfs/literature/an/an496.pdf
the internal oscillator has a wide range between 55 to 116MHz. This indicate a large variation between devices, temperature, process. I wouldn't recommend using it (due to it's unpredictability) unless you are absolutely sure that your system (including devices sending data to and receive data from the Max device) can handle such large variation. - Altera_Forum
If you hadn't told me that I'd have assumed I could chose a frequency between 55 and 116MHz, because that AN you posted (and the short description of the MAX 10 internal oscillator I've read) doesn't make it clear at all, at least to me, that what I'd actually get would be just a frequency within that range. I even added the Internal Oscillator IP to my project, and there's a CLOCK_FREQUENCY constant inside it set to 116. I was assuming I could change it to the frequency I need, expecting of course some error for being an RC oscillator.
But yeah, the MAX 10 datasheet says, on page 30, that for the 10M02 device I'll get a frequency of minimum 55, typical 82, and maximum 116MHz. They really should say this out loud on the AN496, and on the datasheet as well. Even on the features at https://www.altera.com/products/fpga/max-series/max-10/features.html because who'd be expecting such a wide variation? - Altera_Forum--- Quote Start --- MAX 10 10M02. It has all the RAM I need supporting dual port mode, needs only one single 3.3V supply (instead of 3 different voltages that the Cyclone IV needs) --- Quote End --- Beware that that only applies to the "single supply" versions of the MAX10 - "S" in the partnumber after the size - which in turn are only available in certain package options. So for your job you could use the 10M02SCE144C8G (144 QFP package), but not the 10M02DCV36C8G (36-pin tiny package, but only available in "dual supply"). Note also that the MAX10 "dual" supply is "dual" in the same way as Cyclone 3/4 are "dual" supply - actually 3 different voltages needed unless your I/O voltage happens to be the same as one of the internal voltages.
- Altera_Forum--- Quote Start --- Beware that that only applies to the "single supply" versions of the MAX10 - "S" in the partnumber after the size - which in turn are only available in certain package options. So for your job you could use the 10M02SCE144C8G (144 QFP package), but not the 10M02DCV36C8G (36-pin tiny package, but only available in "dual supply"). Note also that the MAX10 "dual" supply is "dual" in the same way as Cyclone 3/4 are "dual" supply - actually 3 different voltages needed unless your I/O voltage happens to be the same as one of the internal voltages. --- Quote End --- Ah thanks. Yes, the chip I'm using is the 10M02SCE144C8G. I did originally intend to go with the 10M02DCV36C8G, since it's cheaper and will do what I need. But the BGA pitch did scare me... /blush But since you mentioned I/O voltages, I see on the MAX 10 datasheet that the recommended VCCIO voltage for all banks should be 3.135V...3.465V for a 3.3V core voltage. I originally imagined that if I set VCCIO2 to, lets say, 2V, and VCCIO3 to 2.5V, all I/O's on bank 2 will output 0V for logic state 0 and 2V for logic state 1, and the I/O's on bank 3 will output 0V and 2.5V. But confirming: this is not true, right? Actually, I originally imagined that I could set a VCCIO to even 5V, and it'd go 0V and 5V. It'd be nice, but, oh well... Also, currently I'm using external drivers/buffers ICs to drive some 3.3V signals out of the FPGA because those signals go outside the board, thru a cable, into another board. And I don't want to put this load on the FPGA. Is this a waste of resources? Can the FPGA outputs indeed drive those signals strongly enough to overcome the impedances/capacitances of the path to the next board? The cable isn't that long. It can be from 10cm to 50cm, and it ends on drivers/buffers inputs.
- Altera_Forum--- Quote Start --- But since you mentioned I/O voltages, I see on the MAX 10 datasheet that the recommended VCCIO voltage for all banks should be 3.135V...3.465V for a 3.3V core voltage. --- Quote End --- That's not how I read the datasheet - I think it means that if you have selected 3V3CMOS as the I/O standard for those pins, then VCCIO must be in that range; similarly for all the other standards. --- Quote Start --- I originally imagined that if I set VCCIO2 to, lets say, 2V, and VCCIO3 to 2.5V, all I/O's on bank 2 will output 0V for logic state 0 and 2V for logic state 1, and the I/O's on bank 3 will output 0V and 2.5V. But confirming: this is not true, right? --- Quote End --- The behaviour isn't defined for random voltages (though it would probably work), only where you pick an I/O standard in the compiler and then supply the matching voltage on VCCIO. But you should be able to use multiple I/O voltages even on a single supply part (though personally I've only done so on the dual supply parts - IMO, the main use of the single supply parts is when the whole system is 3V3). --- Quote Start --- Actually, I originally imagined that I could set a VCCIO to even 5V, and it'd go 0V and 5V. It'd be nice, but, oh well... --- Quote End --- 5V is well outside permitted range and will probably destroy the part... --- Quote Start --- Also, currently I'm using external drivers/buffers ICs to drive some 3.3V signals out of the FPGA because those signals go outside the board, thru a cable, into another board. And I don't want to put this load on the FPGA. Is this a waste of resources? Can the FPGA outputs indeed drive those signals strongly enough to overcome the impedances/capacitances of the path to the next board? The cable isn't that long. It can be from 10cm to 50cm, and it ends on drivers/buffers inputs. --- Quote End --- Outputs are quite strong; more of a concern in that sort of setup is meeting the overshoot requirements on any inputs that you also intend to connect to a long cable.
- Altera_Forum
Oh thanks. Good to know the outputs of the FPGA are indeed strong. As for the other end, it has input ICs that can take quite a beating. I'll consider removing the drivers off my end.
