MAX-10 FPGA, Voltage level on PLL_CLKOUT pins

Hi all,

I want to use one of the PLL_CLKOUT pins on the 10M50DAF256 FPGA to output a clock signal to an external ADC component that requires 1.8V voltage level.

If for example I will use the pin "IO_6_D14/PLL_R_CLKOUTP/DIFFIO_RX_R69P" as a PLL output (PLL_R_CLKOUTP), will the voltage level of my clock be the same as for I/O bank 6, or will it be 1.2V as the VCCD_PLL supply voltage?

Best regards,

Vadim.