Honored ContributorHi,
In MAX 10 FPGA, when the CFM will program ? What are the signals are related to flash ? CONFIG_SEL pin is used to select the CFM0 and CFM1 but, how the process will work ? Please explain if anyone knows. Thanks in advance. Regards, KVL
Honored ContributorI think you need to explain exactly what you're trying to do. Referring to your last post and this one, I'm not sure you understand the purpose of the CFM. It's used to store your MAX 10 FPGA's design.
From the document I pointed you at last time: --- Quote Start --- You need to program the configuration data into the configuration flash memory (CFM) before internal configuration can take place. The configuration data to be written to CFM will be part of the programmer object file (.pof). Using JTAG In-System Programming (ISP), you can program the .pof into the internal flash. --- Quote End --- Cheers, AlexHonored ContributorActually, I'm planning to use USB (via FTDI) to program the internal flash. I am confusing with how data and control signals are connected in between FTDI and FPGA to program the CFM.
Honored ContributorWithout specific logic implemented in the MAX10, JTAG is the only interface available for flash programming. Quartus only supports flash programming through Altera programming adapter, but it's possible to use generic JTAG programming files with third party tools. Some may be able to implement a JTAG programmer through FTDI USB adapter.
The other option is use a dual flash configuration and program the application part of the flash in remote system upgrade mode. The data can be streamed to the MAX10 device via any interface of your choice, e.g. UART. Both options are discussed in detail in the MAX10 handbook chapter "MAX 10 FPGA Configuration Design Guidelines".Honored ContributorYou program the CFM via JTAG. You can't program the internal FLASH directly from other pins. So, an FDTI device won't help you.
Cheers, AlexHonored ContributorThank you FvM and Alex.
Now, I understood and I have another doubt regarding USB Blaster. In USB Blaster circuitry, CPLD is necessary to use ?Honored ContributorThe header is placed between FTDI and CPLD (USB Blaster circuit). What is the purpose of that header ? please clarify.
Honored ContributorYes. The CPLD is essential. The unpopulated header is for programming it. What's programmed into it is a closely guarded Altera secret. Don't expect to be able to replicate it.
Cheers, AlexHonored ContributorOkay. Thank you Alex.
Honored ContributorMay I know what is the purpose of CPLD ? It would be great if anyone clarifies my doubt.
Regards, LakshmiHonored ContributorIt generates the programming signals (JTAG or PS) based on the data from the FTDI device.
Cheers, Alex
