mapping a port to several signals

Hi all!

I have got an issue, I don't really know if it's a bug from ModelSi or an error from my code.

Maybe soeone will be able to tell me...

A/° I am using:

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ModelSim DE 6.6a

Revision: 2010.03

Date: Mar 19 2010

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B/° This code works:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
end entity test;
architecture behavioural of test is
    
    component foo
    port
    (
        s : out std_logic_vector(31 downto 0)
    );
    end component foo;
    
    constant K : natural range 1 to 31 := 15;
    
    signal msb : std_logic_vector(31 downto K);
    signal lsb : std_logic_vector((K - 1) downto 0);
    
begin
    
    foo_inst : foo
    port map
    (
        s(31 downto K)      => msb,
        s((K - 1) downto 0) => lsb
    );
    
end architecture behavioural;

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ModelSim> vcom -reportprogress 300 -work work /home/reinauld/Bureau/test.vhd

# Model Technology ModelSim DE vcom 6.6a Compiler 2010.03 Mar 19 2010

# -- Loading package standard

# -- Loading package std_logic_1164

# -- Loading package numeric_std

# -- Compiling entity test

# -- Compiling architecture behavioural of test

ModelSim>

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C/° I tried to replace the constant K with e generic that I can set when starting the simulation, but it does not work

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
    generic
    (
        K : natural range 1 to 31 := 15
    );
end entity test;
architecture behavioural of test is
    
    component foo
    port
    (
        s : out std_logic_vector(31 downto 0)
    );
    end component foo;
    
    signal msb : std_logic_vector(31 downto K);
    signal lsb : std_logic_vector((K - 1) downto 0);
    
begin
    
    foo_inst : foo
    port map
    (
        s(31 downto K)      => msb,
        s((K - 1) downto 0) => lsb
    );
    
end architecture behavioural;

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ModelSim> vcom -reportprogress 300 -work work /home/reinauld/Bureau/test.vhd

# Model Technology ModelSim DE vcom 6.6a Compiler 2010.03 Mar 19 2010

# -- Loading package standard

# -- Loading package std_logic_1164

# -- Loading package numeric_std

# -- Compiling entity test

# -- Compiling architecture behavioural of test

# ** Error: /home/reinauld/Bureau/test.vhd(29): (vcom-1024) Individually associated formal "s" must be identified with a locally static name.

# ** Error: /home/reinauld/Bureau/test.vhd(30): (vcom-1024) Individually associated formal "s" must be identified with a locally static name.

# ** Error: /home/reinauld/Bureau/test.vhd(30): (vcom-1048) Non-locally static choice (association# 2, choice# 1) is allowed only if it is the only choice of the only association.

# ** Error: /home/reinauld/Bureau/test.vhd(33): VHDL Compiler exiting

# /opt/modelsim_de/modelsim_dlx/linuxpe/vcom failed.

ModelSim>

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Can anyone comment this? Maybe suggest another way to achieve what I try to do?

The point is to map output of a signal driver (that reads stimuli from a file) to several stimuli signals.

Thanks,

Julien