Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

mapping a port to several signals

Hi all! I have got an issue, I don't really know if it's a bug from ModelSi or an error from my code. Maybe soeone will be able to tell me... A/° I am using: --- Quote Start --...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The VHDL standard doesn't provide the option to connect variable bits or slices of port signal individually. But it's easy to connect s as a whole to a wire signal and individual slices of it as intended.