mapping a port to several signals

@kaz:

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The compiler needs to settle what to connect to what i.e. k must be a constant per build

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a generic is set at compilation time, so it behaves like a constant. It's not a signal that can vary in time...

@FvM:

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The VHDL standard doesn't provide the option to connect variable bits or slices of port signal individually

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yes it does (one proof is that 1st version of code compiles)

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But it's easy to connect s as a whole to a wire signal and individual slices of it as intended.

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True :)

@kaz

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use:

generic(

k : integer := 15

);

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This does not change anything...