New Contributor
New ContributorAlso if possible we would want the pin delay information to support DDR layout. this may be in an available document but I haven't found it yet!
Regular ContributorHi Ben Strawbridge,
You look into this page : Quality & Reliablity
Regards,
Fakhrul
New ContributorHello, I have already looked at the drawing that is available.
Regular ContributorHi benstrawbridge,
Could you try check the following. I attached here for two package codes R24C & R24D for Drawing No.M67981:
Intel Agilex® 7 F-Series Device Allegro* PCB Footprint for R24D (2340D) Package - PRELIMINARY
Intel Agilex® 7 F-Series Device Allegro* PCB Footprint for R24C (2340A) Package - PRELIMINARY
Regular ContributorAs we haven't received a response to our previous notification, this thread will be transitioned to community support. We hope all your concerns have been addressed. If you have any new questions, please feel free to open a new thread to receive support from Altera experts. Otherwise, community users will continue to assist you here. Thank you.
