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Altera_Forum's avatar
Altera_Forum
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14 years ago

m25p26

Hi everybody,

I have finished a pcb design with a cyclone III Ep3c25q240, it is configurated in AS mode. There are two connector (10 pins), one for the JTAG and the other for the AS. When I download the .sof file into the FPGA (in JTAG mode with the JTAG connector and the usb blaster cable) there is no problem, but when I try to run the nios2 app it says it cannot reset the nios uP. Also, when I try to configure the flash (m25p16) with the .pof file there is no movement in te configuration progress bar in the quartus2 programmer (in AS mode with the AS connector and the usb blaster cable).

Any help?

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  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    There could be a number of reasons that make the application crash or the CPU freeze.

    First ensure that no part of your application resides in the DDR. This includes heap and stack. If any of those are in the DDR the CPU will erase them while running the memory test.

    Check also that the address you enter is the right one (but I guess you already checked that).

    You can put some signaltap probes on the DDR controller's Avalon interface to see if it's doing anything during the test.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I have debug the mem_test app and it stops when it's made an IORD in the ddr. I also have test the app with the signaltap but it doesn`t seem that it's working properly.

    I think it could be a problem with the memory presets or maybe with the sttl2-standard. I use a serial resistance of 10 ohm (in dq pins) and 22 ohm (the rest ddr pins) for the driver; and 56 ohm attached to 1.25V in the load. ( I have omitted this bus termination for ras,cas,we,dm, ck, and dqs signals)

    Thankyou in advance.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I have no experience with DDR memories unfortunately so I can't help you there.

    With SignalTAP you can at least check if the DDR controller is stalling the CPU with the waitrequest signal.

    Did you check the I/O timing constraints, and that timequest doesn't complain about timing?

    Altera also has a memory interface debugging document (http://www.altera.com/literature/hb/external-memory/emi_debug_hw.pdf), you may find ideas there.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    When I try to debug the ddr commands with signaltap, some illegal and missing sources appear:

    basic_sopc:inst2|altmemddr_0:the_altmemddr_0|mem_cas_n

    basic_sopc:inst2|altmemddr_0:the_altmemddr_0|mem_ras_n

    basic_sopc:inst2|altmemddr_0:the_altmemddr_0|mem_we_n

    " DDIO I/O pins cannot be tapped directly. Tap the hi/lo channels separately."

    and

    basic_sopc:inst2|altmemddr_0:the_altmemddr_0|mem_cke

    basic_sopc:inst2|altmemddr_0:the_altmemddr_0|mem_cs_n

    "The pre-synthesis tap must be preserved by Analysis & Synthesis before it can be tapped. Set the partition's netlist type to Source and recompile."