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hariprasathb's avatar
hariprasathb
Icon for New Contributor rankNew Contributor
6 months ago

LVDS TX/RX Pin Assignment Error in Quartus – Unable to Resolve

Hi Team,   I am facing a pin assignment issue with LVDS TX and RX IP in Quartus Prime. I have tried all the suggestions provided earlier (bank selection, I/O standard, refclk, PLL connections, and...
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AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
6 months ago

Hi Hari,

 

Can you try to remove all the pin assignments?

 

If this passes the compilation, then you should follow the pin placement suggested by the fitter, and then it should be good.

 

It might be the issue with your differential pin and PLL pin placement. Refer guideline below:

https://docs.altera.com/r/docs/721819/25.3.1/agilextm-7-lvds-serdes-user-guide-f-series-and-i-series/pin-placement-for-differential-channels

 

Regards,
Aqid