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yossik
New Contributor
New ContributorLVDS SERDES rx_inclock idle
Hi, We are using LVDS SERDES IP as a multichannel LVDS receiver in Cyclone 10 GX device. The reciver is configured to run at DDR mode using 200MHz rx_inclock. The transmitter device output clock is ...
yossikNew Contributor
New ContributorHi,
This is a design already used in mass production products, it is not that simple to update the design.
As i understand from Altera LVDS SERDES IP Core User Guide, rx_inclock goes into I/O PLL and the designer has not much say about this. I'm adding screenshots from my LVDS SERDES IP settings.
