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yossik
New Contributor
New ContributorLVDS SERDES rx_inclock idle
Hi, We are using LVDS SERDES IP as a multichannel LVDS receiver in Cyclone 10 GX device. The reciver is configured to run at DDR mode using 200MHz rx_inclock. The transmitter device output clock is ...
FvM
Super Contributor
Super ContributorHi,
PLL reference clock must be continuous, PLL isn't able to lock to a gated clock immediately.
Your signal description suggests that the discontinuous clock send along with LVDS data can be used to sample the data directly without a PLL. 200 MHz DDR clock (400 MBPS) isn't particularly fast, Cyclone 10 GX should be able to receive it through GPIO DDR registers and deserializer in core logic.
Can you show exact relation of tx clock and data?
Regards
Frank
