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Altera_Forum
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13 years ago

LVDS_RX and ADC

I'm using an AFE5808EVM from TI. It is an 8 channel ADC that utilizes LVDS to offload sampled data. The clock rate is 40MHz, adc resolution is 12bit.

I set up an LVDS_RX megafunction with the following specs:

data rate = 480mbs ( 12bit * 40MHz)

clock rate = 40MHz

My data clock is 90deg out of phase with the data so I also set that in the LVDS block.

Attached below is the output of the megafunction in signaltap. My signaltap clock is the frame clock from the ADC. (40MHz/12). The test waveform is supposed to be a ramp, but im getting some crazy noise. Fooling around with LVDS terminations doesn't seem to change anything.

Thanks

Matt

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Frame signal for what? Theres the frame signal from the ADC, and the frame signal that is created by the LVDS_RX block. Could it be something to do with the way I assign LVDS pins? This is driving me crazy.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    It could be a clock phase issue. Be sure that signaltap is running on the clock that the data from the ADC is registered on. Also, you may try changing the phase you register the data from the ADC. Try 180, 270, and even in-phase with the clock to the ADC.

    It probably isn't noise on the lvds lines (although I can't rule it out 100%).
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    1. As captainliuy said, try to connect frame clock from ADC to LVDS_RX megafunction, because now I can see (in attached screenshot) you are using bit clock.

    2. Have you constrained properly this project? Cause I had similar problem. When I constrained LVDS part the problem was gone. (I used frame clock)

    3. You are sure, there are no errors on PCB?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    Frame signal for what? Theres the frame signal from the ADC, and the frame signal that is created by the LVDS_RX block. Could it be something to do with the way I assign LVDS pins? This is driving me crazy.

    --- Quote End ---

    I just know a little about the LVDS.You can read this page to find some thing (http://www.alteraforum.com/forum/showthread.php?t=32288&page=2). And also you can read the user guid(http://www.altera.com/literature/ug/ug_altlvds.pdf).

    There have two alignment that you need considner.

    1.Bit alignment.Use pll phase adjust to implement.

    2.World alignment.Use frame signal to align the word boundaries of the incoming serial data.

    Good luck.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I don't understand what's the difference beween your "data clock" and "frame" signal in the diagram?

    The ADC frame clock ("slow" clock) would be connected to the RX PLL input and the bit clock ("fast" clock) generated internally. Setting the sampling phase correctly may be another issue.