Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorLVDS_RX and ADC
I'm using an AFE5808EVM from TI. It is an 8 channel ADC that utilizes LVDS to offload sampled data. The clock rate is 40MHz, adc resolution is 12bit. I set up an LVDS_RX megafunction with the f...
Altera_ForumHonored Contributor
Honored ContributorI don't understand what's the difference beween your "data clock" and "frame" signal in the diagram?
The ADC frame clock ("slow" clock) would be connected to the RX PLL input and the bit clock ("fast" clock) generated internally. Setting the sampling phase correctly may be another issue.
