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Altera_Forum
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15 years ago

LVDS resistor termination in Cyclone III

Hello,

I have a design with 2 FPGA (EP3C16F484) linked together with a set of LVDS line.

I use pins in bank 1, 2, 5 an 6.

Should I place a 100ohms resistors on the receiver side, or is it included in the FPGA?

(I have search for this information in datasheet. I have undersand there is no need for resistor on transmitter, but nothing really accurate on receiver side)

Thanks

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    Should I place a 100ohms resistors on the receiver side

    --- Quote End ---

    Yes. The hardware manual is clear about this point.
  • Altera_Forum's avatar
    Altera_Forum
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    Thanks for answering.

    Please could you told me where the hardware manual is clear (is that on page 7-27)?

    I have miss something... and I want to read it carefully.
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    Thanks for answering.

    Please could you told me where the hardware manual is clear (is that on page 7-27)?

    I have miss something... and I want to read it carefully.

    --- Quote End ---

    Page 6-20 of the cyclone III handbook:

    The LVDS standard does not require an input reference voltage, but it does require a

    100-Ω termination resistor between the two signals at the input buffer. An external

    resistor network is required on the transmitter side for top and bottom I/O banks.

    Page 7-8 of the cyclone III handbook:designing with lvds

    Cyclone III device family I/O banks support LVDS I/O standard. The left and right

    I/O banks support true LVDS transmitters. On the top and bottom I/O banks, the

    emulated LVDS transmitters are supported using two single-ended output buffers

    with external resistors. One of the single-ended output buffers is programmed to have

    opposite polarity. The LVDS receiver requires an external 100-Ω termination resistor

    between the two signals at the input buffer.

    Success, Ton
  • Altera_Forum's avatar
    Altera_Forum
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    Hello I am Miguel and working on FPGAs for 4 years.

    I recently found an doubt that I ant to confirm:

    All IO banksfrom Cyclone 3 have dedicated LVDS RECEIVERS and only 1, 2, 5 and 6 have DEDICATED LVDS Transmitters right???

    Thank you in advance.

    Regards

    --- Quote Start ---

    Page 6-20 of the cyclone III handbook:The LVDS standard does not require an input reference voltage, but it does require a

    100-Ω termination resistor between the two signals at the input buffer. An external

    resistor network is required on the transmitter side for top and bottom I/O banks.

    Page 7-8 of the cyclone III handbook:designing with lvds

    Cyclone III device family I/O banks support LVDS I/O standard. The left and right

    I/O banks support true LVDS transmitters. On the top and bottom I/O banks, the

    emulated LVDS transmitters are supported using two single-ended output buffers

    with external resistors. One of the single-ended output buffers is programmed to have

    opposite polarity. The LVDS receiver requires an external 100-Ω termination resistor

    between the two signals at the input buffer.

    Success, Ton

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Hello I am Miguel and working on FPGAs for 4 years.

    I recently found an doubt that I ant to confirm:

    All IO banksfrom Cyclone 3 have dedicated LVDS RECEIVERS and only 1, 2, 5 and 6 have DEDICATED LVDS Transmitters right???

    Thank you in advance.

    Regards

    --- Quote End ---

    Right. Best explained in C-III Device handbook chapter 7: http://www.altera.com/literature/hb/cyc3/cyc3_ciii51008.pdf