Hello I am Miguel and working on FPGAs for 4 years.
I recently found an doubt that I ant to confirm:
All IO banksfrom Cyclone 3 have dedicated LVDS RECEIVERS and only 1, 2, 5 and 6 have DEDICATED LVDS Transmitters right???
Thank you in advance.
Regards
--- Quote Start ---
Page 6-20 of the cyclone III handbook:The LVDS standard does not require an input reference voltage, but it does require a
100-Ω termination resistor between the two signals at the input buffer. An external
resistor network is required on the transmitter side for top and bottom I/O banks.
Page 7-8 of the cyclone III handbook:
designing with lvds Cyclone III device family I/O banks support LVDS I/O standard. The left and right
I/O banks support true LVDS transmitters. On the top and bottom I/O banks, the
emulated LVDS transmitters are supported using two single-ended output buffers
with external resistors. One of the single-ended output buffers is programmed to have
opposite polarity. The LVDS receiver requires an external 100-Ω termination resistor
between the two signals at the input buffer.
Success, Ton
--- Quote End ---