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Altera_Forum
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15 years ago

LVDS resistor termination in Cyclone III

Hello, I have a design with 2 FPGA (EP3C16F484) linked together with a set of LVDS line. I use pins in bank 1, 2, 5 an 6. Should I place a 100ohms resistors on the receiver side, or is it i...
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Altera_Forum
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11 years ago

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Hello I am Miguel and working on FPGAs for 4 years.

I recently found an doubt that I ant to confirm:

All IO banksfrom Cyclone 3 have dedicated LVDS RECEIVERS and only 1, 2, 5 and 6 have DEDICATED LVDS Transmitters right???

Thank you in advance.

Regards

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Right. Best explained in C-III Device handbook chapter 7: http://www.altera.com/literature/hb/cyc3/cyc3_ciii51008.pdf