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Honored ContributorLUT help!!!
I have wrote this code for implementing a neural network.What it does is to take some values(inputs) and some weights and computes the SUM(values*weigths).What i want to do is to check if the total sum(values*weights)< threshold and correct the weights in order to sum(values*weights)>=threshold.I think that i have to store the weights on a look up table and change the values in order to sum(values*weights)>=threshold.How i can do this?.My code is :
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_SIGNED.ALL; ENTITY ANN IS GENERIC ( m : INTEGER := 4; -- Number of inputs or weights b : INTEGER := 8); --Number of bits per input or weight PORT ( x1,x2,x3,x4: IN UNSIGNED(b-1 DOWNTO 0); w : IN UNSIGNED(b-1 DOWNTO 0); clk: IN STD_LOGIC; y : buffer UNSIGNED(2*b-1 DOWNTO 0); id : buffer bit); END ANN; ARCHITECTURE NEURAL OF ANN IS TYPE weights IS ARRAY (1 TO m) OF UNSIGNED(b-1 DOWNTO 0); TYPE inputs IS ARRAY (1 TO m) OF UNSIGNED(b-1 DOWNTO 0); BEGIN PROCESS(clk,w,x1,x2,x3,x4) VARIABLE weight : weights; VARIABLE input : inputs; VARIABLE prod,acc : UNSIGNED(2*b-1 DOWNTO 0); VARIABLE sub : UNSIGNED(2*b-1 DOWNTO 0); BEGIN IF (clk'EVENT AND CLK='1') THEN weight:=w&weight(1 TO m-1); END IF; input(1):=x1; input(2):=x2; input(3):=x3; input(4):=x4; acc:=(OTHERS=>'0'); FOR j IN 1 TO m LOOP prod:=input(j)*weight(j); acc:=acc+prod; END LOOP; y<=acc; END IF; END PROCESS; END NEURAL;70 Replies
Altera_ForumFor reference, the above two bits of code produce exactly the same bits of hardware.
For your question - yes you can - that is exactly what VHDL is for. On each clock edge you sample the inputs at that instant in time. This will NOT do a rolling accumulate though, if thats what you indented to do. There is no memory from clock cycle to clock cycle.- Altera_Forum
In the example code that you wrote can these inputs change from clock to clock?I mean that this thing i have to do it for 10 times for example with different inputs each time.Can i do this?Thank you
- Altera_Forum
or even more simply:
process(clk) variable sum : integer range 0 to 1023; begin if rising_edge(clk) then if load = '1' then output <= X1+X2+X3+X4; end if; end if; end process; - Altera_Forum
yes, have 4 inputs, and sum them
process(clk) variable sum : integer range 0 to 1023; begin if rising_edge(clk) then if load = '1' then sum := X1 + X2; sum := sum + X3; sum := sum + X4; output <= sum; end if; end if; end process; - Altera_Forum
I want in each clock cycle to insert 4 values and compute the sum of them.Is there a better way to implement it?Thanks again
- Altera_Forum
In your loop you have 4 values. Are you planing on 2*X1 + 2*X2?
you are still thinking VHDL is a programming langauge. The way you are using it is not really correct. Please try and work out the digital hardware before writing the VHDL. - Altera_Forum
Thanks for the quick response.I will try with a second input.But if i use a second input so there is no need to use the loop statement.Am i right?
- Altera_Forum
X1 cannot change during 1 clock cycle. You will need another input if you want a separate value at the same time.
- Altera_Forum
As i said i set in the simulation for x1 to take 2 values in each clock.Then i store these values on the array i declared and i also want to compute the sum of these 2 values.Any ideas how can i change the code to do this thing?Thanks for the help
- Altera_Forum
All I see in this code is on every clock you do 4*X1
