LUT help!!!

--- Quote Start ---

Ignoring that elephant in the room, your code doesn't make sense anyway.

VHDL "variables" are, let's say, temporary things: they are created each time a "process" is triggered.

Which means, for exameple, that "count" will always be "1" -- the "count := count + 1" statement will not carry on to the next clock cycle.

--- Quote End ---

Not true. variables are created once (at elaboration time, not each time the process is triggered), and then updated over and over like anything else. Its all about where you place the variables in the code that makes the difference. for example (inside a clocked process):

a := input

output <= a;

connects a wire between input and output

output<= a;

a := input;

puts a register between the input and the output. If the variable didnt store the values between clocks (as you suggest) then the output would be unconnected all the time. if you do the same thing with signals:

a <= input;

output <= a;

is exactly the same as:

output <= a;

a <= input;

(they both place a register between input and output)

This is why you have to be seriously careful with variables, because unlike signals, the procedural placement is very important.

--- Quote Start ---

This was an example that's why i don't declare an output.As far the result of this code is correct.And the count statement also works.Do you have any suggestion on how to do this(what i described in the previous post)?

--- Quote End ---

What you wrote will work.

rbugalho is very correct though when it comes to resource usage. your code would map to ALOT of memories with alot of wasted memory (ie memory you can no longer access AT ALL). This is the problem when you dont understand the underlying hardware - it becomes very inneficient and very wasteful!

Theres a difference between getting advice and someone doing the work for you:

My advice : learn digital logic if you want to code it yourself. If you want us to do it for you, then pay someone (I charge $50/hour)

My personal opinion about preserved variables: They are rather bad coding style, because the primary purpose of variables is different, but they work obviously. Altera is using them by the way in the Quartus VHDL templates counter example.

Triggerman's storage problem has been finally clarified. I think, it's no necessary to spoonfeed more detailed examples of RAM versus regsister storage. It's more effective to evaluate the basic options and their limitations by making Quartus compile some test code. As said, the test designs must have output signals (that actually depend on stored data somehow), otherwise the results are void.

--- Quote Start ---

Not true. variables are created once (at elaboration time, not each time the process is triggered), and then updated over and over like anything else. Its all about where you place the variables in the code that makes the difference. for example (inside a clocked process):

a := input

output <= a;

connects a wire between input and output. output is a register

output<= a;

a := input;

puts a register between the input and the output. a and output are registers. If the variable didnt store the values between clocks (as you suggest) then the output would be unconnected all the time. if you do the same thing with signals:

a <= input;

output <= a;

is exactly the same as:

output <= a;

a <= input;

(they both place a register between input and output)

This is why you have to be seriously careful with variables, because unlike signals, the procedural placement is very important.

--- Quote End ---

i added some bolded comments for clarity. i understand that you are trying to explain variables, but "connects a wire between input and output" seemed confusing and i wanted to clear things up.

--- Quote Start ---

I think that the more important difference between variables and signals is that variables can only be put into process and that variables are being updated immediately.Thats why i used variables in my code wherever i considered them as necessary.

--- Quote End ---

This is why you need to go and learn VHDL and digital design.

Variables can go in any process, function or procedure. Shared variables can even go in the architecture like signals (but you can forget about those until you have learned VHDL properly!) and are updated immediatly.

The fact they update immediatly is of no importance for what you are doing. it has been recommended time and time again that you use signals. They behave more like real hardware, and you keep talking about more efficient implementation. First stop - forget about variables completly. YOU DO NOT NEED THEM!