Forum Discussion
Honored Contributorlpm_ff megafunction
I am analyzing an old design of an FPGA that looks like it is clocking data in with the lpmFF megafunction set up as a D flip flop. But looking at the input data with an analyzer, the input data goes valid after the rising edge of the clock input to the megawizard flip flop so it seems like a D flip flop would not work properly. Typically a D flipflop sets the output to the input on the rising edge of the input clock. Just wondering if there is a way to set up the lpm_FF megafunction to have the output follow the input when the clock signal is high and then latch the output when clock goes low as perhaps this is what is going on? Also is there a way to simulate what the design will do by entering simulated input signals?
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Altera_Forumthanks for the additional information, I will look at the setup and hold times. I was thinking that for example if the input data to the D flip flop is a 1, it would have to be set high by the time the rising edge of the clock arrived to the D flip flop in order for the output Q to be driven high. I have
******** ******** clk in ** ******** ****** ** data in ***** ******************* So to me it looked like the data whould not be clocked in by the FF.- Altera_Forum
Thats normal. The delay is from the set-up time of the data. Ie, it changed at this rising edge of the clock on the previous register, and at this register it will be clocked on the next clock edge. Are you having problems with setup and hold times?
- Altera_Forum
Thanks for the response, just looking at the data that is feeding into the megafunction it looks like a D flip flop operation would not clock the data in properly, again this is an existing design. The data feeding into the megafunction has the clock go high with data arriving after the rising edge of the clock.
- Altera_Forum--- Quote Start --- I am analyzing an old design of an FPGA that looks like it is clocking data in with the lpmFF megafunction set up as a D flip flop. But looking at the input data with an analyzer, the input data goes valid after the rising edge of the clock input to the megawizard flip flop so it seems like a D flip flop would not work properly. Typically a D flipflop sets the output to the input on the rising edge of the input clock. Just wondering if there is a way to set up the lpm_FF megafunction to have the output follow the input when the clock signal is high and then latch the output when clock goes low as perhaps this is what is going on? Also is there a way to simulate what the design will do by entering simulated input signals? --- Quote End --- Hi, what exactly is your problem ? The FF behaves in the right way. After a short time behind the rising edge of the clock ( clock-to-output delay) the output will change to input value. Kind regards GPK
