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Altera_Forum
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15 years ago

lpm_ff megafunction

I am analyzing an old design of an FPGA that looks like it is clocking data in with the lpmFF megafunction set up as a D flip flop. But looking at the input data with an analyzer, the input data goe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

thanks for the additional information, I will look at the setup and hold times. I was thinking that for example if the input data to the D flip flop is a 1, it would have to be set high by the time the rising edge of the clock arrived to the D flip flop in order for the output Q to be driven high. I have

******** ********

clk in ** ******** ******

**

data in ***** *******************

So to me it looked like the data whould not be clocked in by the FF.