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Altera_Forum
Honored Contributor
Honored Contributorlpm_ff megafunction
I am analyzing an old design of an FPGA that looks like it is clocking data in with the lpmFF megafunction set up as a D flip flop. But looking at the input data with an analyzer, the input data goe...
Altera_ForumHonored Contributor
Honored ContributorThats normal. The delay is from the set-up time of the data. Ie, it changed at this rising edge of the clock on the previous register, and at this register it will be clocked on the next clock edge. Are you having problems with setup and hold times?
