Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorlpm_ff megafunction
I am analyzing an old design of an FPGA that looks like it is clocking data in with the lpmFF megafunction set up as a D flip flop. But looking at the input data with an analyzer, the input data goe...
Altera_ForumHonored Contributor
Honored ContributorThanks for the response, just looking at the data that is feeding into the megafunction it looks like a D flip flop operation would not clock the data in properly, again this is an existing design. The data feeding into the megafunction has the clock go high with data arriving after the rising edge of the clock.
