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Altera_Forum
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14 years ago

Low Frequency PLL Multiplier

For a video genlocking application I need to multiply an incoming ~15KHZ clock by ~2000 to produce ~30MHZ. The input frequency is too low for the PLLs in my Cyclone III and I've been straining my brain trying to come up with a clever way to use them. The alternative is to use an external PLL. Any ideas?

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  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Depends on your requirements for the 30 MHz clock. If you can accept larger jitter for it, a regular all-digital PLL can be solution. Alternatively, a quasi-continuous digital PLL (jitter < 0.5 ns) can be build using the PLL dynamic phase shift feature, but the lock range will be limited.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks for your thoughts. I've heard of an all digital PLL but know little about it. Seems like it would need to run from a clock much higher than 30MHZ. I can research this one. I think I can tolerate 1-2 ns of jitter.

    I've not heard of the quasi-continuous digital PLL, can you point me to a reference?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    Seems like it would need to run from a clock much higher than 30MHZ. I can research this one. I think I can tolerate 1-2 ns of jitter.

    --- Quote End ---

    A reasonable core clock for the clock generator module can be 200 - 300 MHz maximum with Cyclone FPGAs. So 1 -2 ns jitter isn't achievable by a regular digital PLL. You would need to use a multi-phase input clock for a finer phase resolution. Should be basically possible.

    The dynamic phase shift feature allows to shift a PLL clock in increments of 1/8 of the VCO period, at a rate of about 20 MHz. If you don't need the fine phase resolution, you can program larger phase steps in the PLL setup.

    Locking a variable delay unit to an input frequency is usually designated DLL (delay locked loop) in contrast to a PLL, that uses a variable frequency oscillator.

    At maximum phase resolution, the dynamic phase shift method allows a frequency variation of several +/- 100 ppm which is suffcient to lock on a crystal based input frequency.

    There's no IP core or reference design for a dynamic phase-shift based PLL provided by Altera.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I neglected to mention that the required lock range is +/- 5%, so it seems the dynamic phase shift approach would not be adequate in this regard. If I got some relief on the jitter specification, say 3-5 ns, maybe the all digital PLL would work. I'm just guessing at this point that a 300 MHZ core clock would yield something like 10% jitter at 30 MHZ.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    With a 300 MHz clock, the jitter can be as low as +/- 1.7 ns. You can further increase the phase resolution by combining multiple phase shifted clocks and working on both clock edges. But of course, the design becomes more complex and timing closure difficult.