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Altera_Forum
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14 years ago

Low Frequency PLL Multiplier

For a video genlocking application I need to multiply an incoming ~15KHZ clock by ~2000 to produce ~30MHZ. The input frequency is too low for the PLLs in my Cyclone III and I've been straining my br...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I neglected to mention that the required lock range is +/- 5%, so it seems the dynamic phase shift approach would not be adequate in this regard. If I got some relief on the jitter specification, say 3-5 ns, maybe the all digital PLL would work. I'm just guessing at this point that a 300 MHZ core clock would yield something like 10% jitter at 30 MHZ.