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Seems like it would need to run from a clock much higher than 30MHZ. I can research this one. I think I can tolerate 1-2 ns of jitter.
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A reasonable core clock for the clock generator module can be 200 - 300 MHz maximum with Cyclone FPGAs. So 1 -2 ns jitter isn't achievable by a regular digital PLL. You would need to use a multi-phase input clock for a finer phase resolution. Should be basically possible.
The dynamic phase shift feature allows to shift a PLL clock in increments of 1/8 of the VCO period, at a rate of about 20 MHz. If you don't need the fine phase resolution, you can program larger phase steps in the PLL setup.
Locking a variable delay unit to an input frequency is usually designated DLL (delay locked loop) in contrast to a PLL, that uses a variable frequency oscillator.
At maximum phase resolution, the dynamic phase shift method allows a frequency variation of several +/- 100 ppm which is suffcient to lock on a crystal based input frequency.
There's no IP core or reference design for a dynamic phase-shift based PLL provided by Altera.
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