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Altera_Forum
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14 years ago

Low Frequency PLL Multiplier

For a video genlocking application I need to multiply an incoming ~15KHZ clock by ~2000 to produce ~30MHZ. The input frequency is too low for the PLLs in my Cyclone III and I've been straining my br...
Altera_Forum's avatar
Altera_Forum
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14 years ago

With a 300 MHz clock, the jitter can be as low as +/- 1.7 ns. You can further increase the phase resolution by combining multiple phase shifted clocks and working on both clock edges. But of course, the design becomes more complex and timing closure difficult.