Altera_Forum
Honored Contributor
13 years agoloop in VHDL
Hi, I have a question. now there are 3 vector connect with AND gate like this:
C(3)<= A(4) and B(3) C(2)<= A(4)and A(3)and B(2) C(1)<= A(4)and A(3)andA(2)and B(1) C(0)<= A(4)and A(3)andA(2)andA(1)B(0) How can I use loop to describe it?