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Altera_Forum's avatar
Altera_Forum
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14 years ago

loop in VHDL

Hi, I have a question. now there are 3 vector connect with AND gate like this: C(3)<= A(4) and B(3) C(2)<= A(4)and A(3)and B(2) C(1)<= A(4)and A(3)andA(2)and B(1) C(0)<= A(4)and A(3)andA(...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Try something like that 

for   i in 0      to n - 1 loop
  for j in i + 2  to n     loop
    a_res :=  a(j) and a(j - 1);
  end loop;
  c(i)  <=  a_res and b(i);
end loop;
But be aware that it's untested code.

You've to verify it. :)

edit:

That's definitely not it! :(

But I think you've to use nested loops...