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Altera_Forum's avatar
Altera_Forum
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14 years ago

loop in VHDL

Hi, I have a question. now there are 3 vector connect with AND gate like this: C(3)<= A(4) and B(3) C(2)<= A(4)and A(3)and B(2) C(1)<= A(4)and A(3)andA(2)and B(1) C(0)<= A(4)and A(3)andA(...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I think something like that would do the trick

for   i in 0      to n - 1 loop
  a_res := a(n);
  for j in i + 1  to n - 1 loop
    a_res :=  a_res and a(j);
  end loop;
  c(i)  <=  a_res and b(i);
end loop;
Yes the nested loops ides is the right one, you just need to initialize the variable and use it recursively in the inside loop. Don't forget to declare the variable in the process.