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Altera_Forum's avatar
Altera_Forum
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14 years ago

loop in VHDL

Hi, I have a question. now there are 3 vector connect with AND gate like this: C(3)<= A(4) and B(3) C(2)<= A(4)and A(3)and B(2) C(1)<= A(4)and A(3)andA(2)and B(1) C(0)<= A(4)and A(3)andA(...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

with generic code, like:

C(n-1)<= A(n) and B(n-1)

C(n-2)<= A(n)and A(n-1)and B(n-2)

......

C(0)<= A(n)and A(n-1)......and A(1)B(0).

upstair is a example for n=4