Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

loop in VHDL

Hi, I have a question. now there are 3 vector connect with AND gate like this: C(3)<= A(4) and B(3) C(2)<= A(4)and A(3)and B(2) C(1)<= A(4)and A(3)andA(2)and B(1) C(0)<= A(4)and A(3)andA(...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Do you want to write generic code or do you simply want to use a

loop construct on the actual code you've posted?

Using a loop construct on your actual code will make it worse imho.