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Altera_Forum's avatar
Altera_Forum
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13 years ago

LE requirement

Hi,

I like to build a system where I take data from two cameras (standard 10 bit camera interface with 27MHz clock) and write the incoming image data to SDRAM for a period of time. Later I take the images from SDRAM and send to CPU via SPI. (This is after image acquisition is complete). The data will be transparent to FPGA, no involvement of data other than shifting from Cam to Memory, memory to SPI.

I am trying to get a feeling from experts what would be the logic elements and memory requirements would be like? (I have zero FPGA experience but generally good hardware/firmware guy).

I am thinking of using lowest end Cyclone IV E series which has like 6K LEs. (if I build the whole thing in EDA tool and see it that way, it would take me weeks to decide, I like to build the hardware now by taking some calculated risks).

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I'd say it'll fit, but for the first design, take at least 16K. Take the same package, check if all pin matches and replace the part on final design. Usually same package and same series devices are pin-to-pin compatible. Remember to select migration devices in options in case You'll run out of other resources in smaller device even You have enough LEs.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I would go this way:

    1. Calculate required bandwith for the RAM Interface (with overhead for refresh ...)

    The bandwith is speed grade dependent!

    2. Estimate the pin count you need and select an appripriate package

    3. Are there board layout requirements such as ball pitch size or package size?

    5. Have a look at the device datasheet, connection guideline and errata sheet to ensure that there are no limitation in that package that might hurt you, keep them in mind

    4. See what LE densities are availabe and are pin compatible to each other

    5. Instantiate a memory controller that fits your setup in your design using Quartus II. You can leave out the actual timing values, just use a preset and the bit width and put some glue logic around it.

    Use the highest density for your package

    6. Compile and see how much logic the controller itself needs.

    7. If you already have the code for the camera interface, add it to get a better estimation.

    8. Select the device with the LEs you need. Stay below 90% ressource usage to ease timing closure.

    If you need any estimation, I would go for the 10k device (min). But to stay on the safe side, use the highest density for the development and go to the cheaper one for production.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    The SDRAM core is small, about 300LEs, but I am not sure about SGDMA. Plus a bigger device is better for Signaltap.