Hi,
As I understand it, you have some inquiries related to the LDPC decoder simulation. Just would like to check with you if you are referring to LDPC or 5G LDPC IP? Also, what is the specific Quartus version and FPGA device that you are using?
For your information, in both of the IPs, you can try to generate the example design and perform simulation with Modelsim. You may then refer to the simulation to see if can spot any anomaly with your own simulation. You can generate the example design through IP Parameter Editor -> Generate -> Generate Example Design.
To run the simulation in Modelsim, you can do the following:
1. Change the working directory in Modelsim to \mentor in the example design directory
2. Type "source msim_setup.tcl"
3. Type "ld" to start compilation
4. Populate your signals of interest into the waveform
5. "Run -all"
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin