New Contributor
Regular ContributorHi,
As I understand it, you have some inquiries related to the LDPC decoder simulation. Just would like to check with you if you are referring to LDPC or 5G LDPC IP? Also, what is the specific Quartus version and FPGA device that you are using?
For your information, in both of the IPs, you can try to generate the example design and perform simulation with Modelsim. You may then refer to the simulation to see if can spot any anomaly with your own simulation. You can generate the example design through IP Parameter Editor -> Generate -> Generate Example Design.
To run the simulation in Modelsim, you can do the following:
1. Change the working directory in Modelsim to \mentor in the example design directory
2. Type "source msim_setup.tcl"
3. Type "ld" to start compilation
4. Populate your signals of interest into the waveform
5. "Run -all"
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
New ContributorHi,
My Quartus version is Quartus Prime Pro Edition 19.1, FPGA device is Arria 10 10AS066H3F34I2SG. I use LDPC IP which configuration as follows.
Then I follow you steps to generate example design for simulation. However, there is still no output , the simulation screenshot as follows.
My ModelSim version is INTEL FPGA STARTER EDITION 10.6d. Then I use my own instance of the LDPC IP, the simulation as follows.
I think it might be short of some .hex files which save the adjoint matrix for 802.11n decode. How do you think?
Best regards,
Tang
