Altera_Forum
Honored Contributor
18 years agoJTAG Access for ID Read
Hello All ,
I have designed a JTAG controller using FPGA I could verify my write sequence by monitoring TMS and TDO on the scope , All the signal looks fine on the scope And I hope to verify my read sequence by reading the ID from the FPGA Is there anyone who has documents about the sequence and protocol of read ID process in Quartus II programmer ? Thanks very much