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Altera_Forum's avatar
Altera_Forum
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14 years ago

Jitter estimation on Arria II Gx devices

Hi everyone,

I want to estimate jitter on various clocks used in my FPGA design. My device is an Arria II Gx FPGA.

Input clock : 80 MHz

Jitter : 1 ps (RMS)

Output clock 1 : 100 MHz

jitter = ?

How do I determine my ouput jitter at the output of the PLL. In the datahsheet, they say it would be about 300 ps peak-peak when used with a dedicated clock output. So is the dedicated clock output adding the 300 ps peak-peak jitter or is it the dedicated clock output?

I'm asking since I need to cascades 2 PLL and I wouldn't want to have much jitter at the output of my second PLL.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    PLL generated jitter is one source of jitter. Other sources include io effect, reflections, etc. So ideally I would think that PLL spec is about PLL generated jitter in ideal case.

    Two cascaded PLLs do not necessarily add up their jitter because every PLL has jitter tolerance so if the second PLL can bear it it may absorb it otherwise it certainly will make it worse.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thanks for your answer.

    I get a warning for the ALtmemphy DDR-2 controller complaining that the jitter might be too high though...

    I'll have to double check and make sure I will be able to use the DDR-2 with a 100 MHz generated from a PLL compared to one generated from a crystal.